VLSI ARCHITECTURE FOR ERROR DETECTION AND CORRECTION BASED ON XOR AGAINST MULTIPLE CELL UPSETS WITH REDUCED REDUNDANT BITS
Memories are in general protected with error correction codes per word in order to improve its reliability. The errors introduced by the radiation particles on memories will affect more than one cell leading to what is called as Multiple Cell Upsets (MCUs). As technology is scaled down, MCUs bec...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
ICT Academy of Tamil Nadu
2019-04-01
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| Series: | ICTACT Journal on Microelectronics |
| Subjects: | |
| Online Access: | http://ictactjournals.in/paper/IJME_Vol_5_Iss_2_Paper_1_751_757.pdf |