One approach to compact testing of digital circuits
A problem of signature analyzer synthesis with required properties is solved for digital schemes compact testing. The main attention is devoted to the issues of eliminating losses of diagnostic information and to simplicity of structural organization. Solutions are based on detecting all error vecto...
Main Author: | Feofanovich Berezkin Evgeniy |
---|---|
Format: | Article |
Language: | English |
Published: |
Institut za istrazivanja i projektovanja u privredi
2019-01-01
|
Series: | Istrazivanja i projektovanja za privredu |
Subjects: | |
Online Access: | https://scindeks-clanci.ceon.rs/data/pdf/1451-4117/2019/1451-41171901026F.pdf |
Similar Items
-
Reachability Analysis of RTL Circuits Using k-Induction Bounded Model Checking and Test Vector Compaction
by: Roy, Tonmoy
Published: (2017) -
Computation of Compact Distributions of Discrete Elements
by: Jie Chen, et al.
Published: (2019-02-01) -
Local compactness in approach spaces I
by: R. Lowen, et al.
Published: (1998-01-01) -
Static Test Compaction for VLSI Tests An Evolutionary Approach
by: LOGOFATU, D.
Published: (2008-06-01) -
Modeling Subsurface Drainage in Compacted Cultivated Histosols
by: Cedrick Victoir Guedessou, et al.
Published: (2021-01-01)