Design of a Sub-Picosecond Jitter with Adjustable-Range CMOS Delay-Locked Loop for High-Speed and Low-Power Applications

Design of a Sub-Picosecond Jitter with Adjustable-Range CMOS Delay-Locked Loop for High-Speed and Low-Power Applications

A Delay-Locked Loop (DLL) with a modified charge pump circuit is proposed for generating high-resolution linear delay steps with sub-picosecond jitter performance and adjustable delay range. The small-signal model of the modified charge pump circuit is analyzed to bring forth the relationship betwee...

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Bibliographic Details
Main Authors: Bilal I. Abdulrazzaq, Omar J. Ibrahim, Shoji Kawahito, Roslina M. Sidek, Suhaidi Shafie, Nurul Amziah Md. Yunus, Lini Lee, Izhal Abdul Halin
Format: Article
Language:English
Published: MDPI AG 2016-09-01
Series:Sensors
Subjects:
delay step
delay range
time jitter
Delay-Locked Loop (DLL)
charge pump
Capacitor-Reset Circuit (CRC)
Online Access:http://www.mdpi.com/1424-8220/16/10/1593

Internet

http://www.mdpi.com/1424-8220/16/10/1593

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