Multiple-Node Charge Collection in 65 nm Technology Triple-Well SRAMs

• Main Authors: Indranil Chatterjee, NIhar M Mahatme
• Format: Article
• Language: English
• Published: Institute of Technology, Nirma University 2000-01-01
• Series: Nirma University Journal of Engineering and Technology
• Online Access: http://nujet.org.in/index.php/nujet/article/view/105

The conventional CMOS fabrication process can be either a dual-well technology or a triple-well technology. Triple-well technology has been shown to be superior to dualwell technology in terms of electrical performance. However, for advanced deep-sub-micron technologies, reliability concerns over soft errors require a thorough investigation of these technologies. This work presents a comparative analysis of charge-collection mechanisms due to single events caused by ionizing particles in 65 nm dual- and triple-well technologies. Primary factors affecting the charge-collection mechanisms for a wide range of particle energies are investigated for SRAM circuits to show that triple-well technologies are more vulnerable at low LET particles while dual-well technologies are more vulnerable for high LET particles.