Analysis of a Parasitic‐Diode‐Triggered Electrostatic Discharge Protection Circuit for 12 V Applications
In this paper, an electrostatic discharge (ESD) protection circuit is designed for use as a 12 V power clamp by using a parasitic‐diode‐triggered silicon controlled rectifier. The breakdown voltage and trigger voltage (Vt) of the proposed ESD protection circuit are improved by varying the length bet...
| Main Authors: | , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Electronics and Telecommunications Research Institute (ETRI)
2017-10-01
|
| Series: | ETRI Journal |
| Subjects: | |
| Online Access: | https://doi.org/10.4218/etrij.17.0117.0026 |