A variation tolerant data dependent clock gating approach for PSN attenuated low power digital IC
The evolution of semiconductor industry has brought in high current flow across the power rails (‘Vdd’ and ground) of digital integrated circuits (IC) encapsulated by the modern chip packages. This instigates the uncontrollable generation of Power Supply Noise (PSN), along with dynamic and static po...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Elsevier
2019-09-01
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| Series: | Ain Shams Engineering Journal |
| Online Access: | http://www.sciencedirect.com/science/article/pii/S2090447919300383 |