Learning Parity with Physical Noise: Imperfections, Reductions and FPGA Prototype

Learning Parity with Physical Noise: Imperfections, Reductions and FPGA Prototype

Hard learning problems are important building blocks for the design of various cryptographic functionalities such as authentication protocols and post-quantum public key encryption. The standard implementations of such schemes add some controlled errors to simple (e.g., inner product) computations...

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Bibliographic Details
Main Authors: Davide Bellizia, Clément Hoffmann, Dina Kamel, Hanlin Liu, Pierrick Méaux, François-Xavier Standaert, Yu Yu
Format: Article
Language:English
Published: Ruhr-Universität Bochum 2021-07-01
Series:Transactions on Cryptographic Hardware and Embedded Systems
Subjects:
Learning Parity with Noise
Physical Assumptions
Physical Defaults
Security Reductions
FPGA Implementations
Side-Channel Security
Online Access:https://tches.iacr.org/index.php/TCHES/article/view/8979

Internet

https://tches.iacr.org/index.php/TCHES/article/view/8979

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