Multi-<inline-formula> <tex-math notation="LaTeX">${V}_{\text{th}}$ </tex-math></inline-formula> Strategies of 7-nm node Nanosheet FETs With Limited Nanosheet Spacing

• Main Authors: Jun-Sik Yoon, Jinsu Jeong, Seunghwan Lee, Rock-Hyun Baek
• Format: Article
• Language: English
• Published: IEEE 2018-01-01
• Series: IEEE Journal of the Electron Devices Society
• Subjects: 7-nm node; nanosheet FET (NSFET); nanosheet spacing; work-function metal; multi-<italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">Vth</italic>; TiN capping layer
• Online Access: https://ieeexplore.ieee.org/document/8419236/

In this paper, multi-threshold voltage (<i>V</i>_th) scheme of 7-nm node nanosheet FETs (NSFETs) with narrow NS spacing were successfully achieved by metal-gate work function (WF) and channel doping (<i>N</i>_ch) using fully calibrated 3-D TCAD simulations. The limited NS spacing, which allows TiN capping layer only, makes different WF between the edge and the middle part of NS circumference. Unfortunately, this causes non-linear Vth shifts and dc performance degradation as a function of WF due to one-side turn-on phenomena between the edge and the middle part. Furthermore, the fixed WF of TiN capping layer limits Vth shifts toward ultra-low-power applications. To enable multi-Vth of NSFETs, several possible solutions are addressed: changing the Nch and the WF of TiN capping layer. The higher <i>N</i>_ch enables lower off-state current while 50-nm-wide three-stacked NS decreases dc performance variations effectively. Changing the WF of TiN capping layer can extend <i>V</i>_th margins, but degrade DC performance as a trade-off. Nonetheless, 7-nm node NSFETs adopting these techniques have multi-<i>V</i>_th options to satisfy wide ranges from ultra-low-power to high-performance applications.