An Offset-free High linear Low Power High Speed Four-Quadrant MTL Multiplier
In this paper a new CMOS current-mode four-quadrant analog multiplier circuit is proposed. The major advantages of this design are high linearity, high speed and low power consumption. Removing dc offset is the most important improvement in this topology. The circuit is designed with 1.8V supply vol...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Ital Publication
2017-11-01
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| Series: | Emerging Science Journal |
| Subjects: | |
| Online Access: | https://ijournalse.org/index.php/ESJ/article/view/44 |