A Generalized Multilevel Inverter Topology With Reduction of Total Standing Voltage

• Main Authors: Jagabar Sathik Mohamed Ali, Dhafer J. Almakhles, S. A. Ahamed Ibrahim, Saeed Alyami, Sivakumar Selvam, Mahajan Sagar Bhaskar
• Format: Article
• Language: English
• Published: IEEE 2020-01-01
• Series: IEEE Access
• Subjects: Multilevel inverter; inverter; blocking voltage; cascaded structure; reduced power components
• Online Access: https://ieeexplore.ieee.org/document/9187204/

This paper presents a new multilevel inverter topology with reduced active switches and total standing voltage. The proposed topology can generate a high number of voltage levels in the symmetric configuration. This topology intuitively generates positive and negative cycles without an additional H-bridge unit, which considerably reduces the total standing voltage of the inverter. A cascaded structure is developed from the proposed topology to create higher voltage levels. To show the novelty of the proposed topology, a thorough comparison between the available and the proposed topologies in terms of the number of switches, standing voltages, and dc-sources is presented. Furthermore, the power loss analysis is carried out for various load values. The feasibility of the proposed nine-level inverter is verified with simulation and experimental results.