A Generalized Multilevel Inverter Topology With Reduction of Total Standing Voltage

A Generalized Multilevel Inverter Topology With Reduction of Total Standing Voltage

This paper presents a new multilevel inverter topology with reduced active switches and total standing voltage. The proposed topology can generate a high number of voltage levels in the symmetric configuration. This topology intuitively generates positive and negative cycles without an additional H-...

Full description

Bibliographic Details
Main Authors: Jagabar Sathik Mohamed Ali, Dhafer J. Almakhles, S. A. Ahamed Ibrahim, Saeed Alyami, Sivakumar Selvam, Mahajan Sagar Bhaskar
Format: Article
Language:English
Published: IEEE 2020-01-01
Series:IEEE Access
Subjects:
Multilevel inverter
inverter
blocking voltage
cascaded structure
reduced power components
Online Access:https://ieeexplore.ieee.org/document/9187204/

Internet

https://ieeexplore.ieee.org/document/9187204/

Similar Items