An Algorithm for Generating Boolean Expressions in VHDL Based on Ladder Diagrams
This study proposes an algorithm for generating the associated Boolean expression in VHDL, given a ladder diagram (LD) as the input. The purpose of the algorithm is to implement of field-programmable gate array- (FPGA-) based programmable logic controllers (PLCs), where an effective conversion from...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Hindawi Limited
2015-01-01
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| Series: | Mathematical Problems in Engineering |
| Online Access: | http://dx.doi.org/10.1155/2015/530586 |