Modeling and Simulation of Network-on-Chip Systems with DEVS and DEUS
Networks on-chip (NoCs) provide enhanced performance, scalability, modularity, and design productivity as compared with previous communication architectures for VLSI systems on-chip (SoCs), such as buses and dedicated signal wires. Since the NoC design space is very large and high dimensional, evalu...
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| Format: | Article |
| Language: | English |
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Hindawi Limited
2014-01-01
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| Series: | The Scientific World Journal |
| Online Access: | http://dx.doi.org/10.1155/2014/982569 |