A Connection Block Implemented in the RTL Design for Delay Time Equalization of Wave-Pipelining
Field-programmable gate arrays (FPGAs) which have many advantages are used in various devices. Use of the FPGAs is not only prototyping and verification of circuits but also an important part of the commercial products. A CPU of hardcore is required in the FPGAs. But it has a problem with the archit...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
International Institute of Informatics and Cybernetics
2016-02-01
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| Series: | Journal of Systemics, Cybernetics and Informatics |
| Subjects: | |
| Online Access: | http://www.iiisci.org/Journal/CV$/sci/pdfs/SA732LL15.pdf
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