An Efficient LUT Design on FPGA for Memory-Based Multiplication

• Main Authors: C. S. Vinitha, R. K. Sharma
• Format: Article
• Language: English
• Published: Iran University of Science and Technology 2019-12-01
• Series: Iranian Journal of Electrical and Electronic Engineering
• Subjects: vlsi design; memory-based architecture; multiplier; fpga design; fir filter; transposed structure; distributed arithmetic.
• Online Access: http://ijeee.iust.ac.ir/article-1-1388-en.html

An efficient Lookup Table (LUT) design for memory-based multiplier is proposed.  This multiplier can be preferred in DSP computation where one of the inputs, which is filter coefficient to the multiplier, is fixed. In this design, all possible product terms of input multiplicand with the fixed coefficient are stored directly in memory. In contrast to an earlier proposition Odd Multiple Storage (OMS), we have proposed utilizing Even Multiple Storage (EMS) scheme for memory-based multiplication and by doing so we are able to achieve a less complex and high-speed design. Because of the very simpler control circuit used in our design, to extract the odd multiples of the product term, we are also able to achieve a significant reduction in path delay and area complexity. For validation, the proposed design of the multiplier is coded in VHDL, simulated and synthesized using Xilinx tool and then implemented in Virtex 7 XC7vx330tffg1157 FPGA. Various key performance metrics like number of slices, number of slice LUT’s and maximum combinational path delay is estimated for different input word length. Also, the performance metrics are compared with the existing OMS design. It is found that the proposed EMS design occupies nearly 62% less area in terms of number of slices as compared to the OMS design and the maximum path delay is decreased by 77% for a 64-bit input. Further, the proposed multipliers are used in Transposed FIR filter and its performance is compared with the OMS multiplier based filter for various filter orders and various input lengths.