An Efficient LUT Design on FPGA for Memory-Based Multiplication
An efficient Lookup Table (LUT) design for memory-based multiplier is proposed. This multiplier can be preferred in DSP computation where one of the inputs, which is filter coefficient to the multiplier, is fixed. In this design, all possible product terms of input multiplicand with the fixed coeff...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Iran University of Science and Technology
2019-12-01
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| Series: | Iranian Journal of Electrical and Electronic Engineering |
| Subjects: | |
| Online Access: | http://ijeee.iust.ac.ir/article-1-1388-en.html |