High-Throughput FPGA-Based Hardware Accelerators for Deflate Compression and Decompression Using High-Level Synthesis

• Main Authors: Morgan Ledwon, Bruce F. Cockburn, Jie Han
• Format: Article
• Language: English
• Published: IEEE 2020-01-01
• Series: IEEE Access
• Subjects: Deflate algorithm; lossless compression; LZ77 compression; hardware accelerator; FPGAbased accelerator; high-level synthesis
• Online Access: https://ieeexplore.ieee.org/document/9050498/

The Deflate compression algorithm provides one of the most widely used solutions for lossless data compression. Field-programmable gate arrays (FPGAs) are commonly used to implement hardware accelerators that speed up computation-intensive applications. In this article, FPGA-based accelerators for Deflate compression and decompression are described. These accelerators were specified in C++ and synthesized using Vivado High-Level Synthesis (HLS) for a Xilinx Virtex UltraScale+ series FPGA and a system clock frequency of 250 MHz. The proposed compressor processes data at a fixed input throughput of 4.0 GB/s and achieves a geometric mean compression ratio of 1.92 on the Calgary corpus benchmark files using static Huffman encoding. While not the first compressor synthesized using high-level synthesis, our design achieves a 25% greater throughput and an 11% greater compression ratio than the only other published design that uses Vivado HLS. The proposed decompressor design achieves average input throughputs of 196.61 MB/s and 97.40 MB/s, for statically and dynamically encoded Calgary corpus files, respectively. This is the first published decompressor design that is synthesized using high-level synthesis and provides performance that is comparable to that of the best published designs, having static throughputs 11% higher and dynamic throughputs only 10% lower than the expertly-optimized design sold by Xilinx.