Comment on “High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs”

Comment on “High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs”

This brief points out some problems when mapping the optimized GPCs using the heuristic of the paper above. A thorough analysis revealed that a significant number of additional LUTs are required to route the signals when mapping the optimized designs on current FPGAs. Taking these resources into acc...

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Bibliographic Details
Main Authors: Martin Kumm, Peter Zipf
Format: Article
Language:English
Published: Hindawi Limited 2016-01-01
Series:International Journal of Reconfigurable Computing
Online Access:http://dx.doi.org/10.1155/2016/3015403
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spelling doaj-914a2b66b5d34c03a2e7c59ae163c52e2020-11-24T23:46:53ZengHindawi LimitedInternational Journal of Reconfigurable Computing1687-71951687-72092016-01-01201610.1155/2016/30154033015403Comment on “High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs”Martin Kumm0Peter Zipf1Digital Technology Group, University of Kassel, 34121 Kassel, GermanyDigital Technology Group, University of Kassel, 34121 Kassel, GermanyThis brief points out some problems when mapping the optimized GPCs using the heuristic of the paper above. A thorough analysis revealed that a significant number of additional LUTs are required to route the signals when mapping the optimized designs on current FPGAs. Taking these resources into account, the optimized GPCs require at least the same resources as previous state of the art.http://dx.doi.org/10.1155/2016/3015403
collection DOAJ
language English
format Article
sources DOAJ
author Martin Kumm
Peter Zipf
spellingShingle Martin Kumm
Peter Zipf
Comment on “High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs”
International Journal of Reconfigurable Computing
author_facet Martin Kumm
Peter Zipf
author_sort Martin Kumm
title Comment on “High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs”
title_short Comment on “High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs”
title_full Comment on “High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs”
title_fullStr Comment on “High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs”
title_full_unstemmed Comment on “High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs”
title_sort comment on “high efficiency generalized parallel counters for look-up table based fpgas”
publisher Hindawi Limited
series International Journal of Reconfigurable Computing
issn 1687-7195
1687-7209
publishDate 2016-01-01
description This brief points out some problems when mapping the optimized GPCs using the heuristic of the paper above. A thorough analysis revealed that a significant number of additional LUTs are required to route the signals when mapping the optimized designs on current FPGAs. Taking these resources into account, the optimized GPCs require at least the same resources as previous state of the art.
url http://dx.doi.org/10.1155/2016/3015403
work_keys_str_mv AT martinkumm commentonhighefficiencygeneralizedparallelcountersforlookuptablebasedfpgas
AT peterzipf commentonhighefficiencygeneralizedparallelcountersforlookuptablebasedfpgas
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