Comment on “High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs”
This brief points out some problems when mapping the optimized GPCs using the heuristic of the paper above. A thorough analysis revealed that a significant number of additional LUTs are required to route the signals when mapping the optimized designs on current FPGAs. Taking these resources into acc...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Hindawi Limited
2016-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2016/3015403 |