An Ultra-Low-Voltage Level Shifter With Embedded Re-Configurable Logic and Time-Borrowing Latch Technique
The increasing number of voltage domains along with the size of the data bus requires an exponential increase in the number level shifter (LS) circuits for signal interfacing, creating an exploding in silicon area and power consumption. Higher area-efficiency can be attained by further improving the...
| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2021-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/9420697/ |