VLSI IMPLEMENTATION OF HIGH SPEED AREA EFFICIENT ARITHMETIC UNIT USING VEDIC MATHEMATICS
High speed Arithmetic Units (AUs) are widely used in architectures used in signal and image processing applications. AUs involve multifunctions and have multiplier as the critical element. In this paper, we present design and implementation of high speed and area efficient AU using Vedic algorith...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
ICT Academy of Tamil Nadu
2016-04-01
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| Series: | ICTACT Journal on Microelectronics |
| Subjects: | |
| Online Access: | http://ictactjournals.in/paper/IJME_V2_I1_paper_5_198_202.pdf |