Analysis of Coplanar On-Chip Interconnects on Lossy Semiconducting Substrates

• Main Authors: M. Stucchi, Roest, D. de, S. Vandenberghe, K. Maex, B. Nauwelaers, H. Ymeri
• Format: Article
• Language: English
• Published: Spolecnost pro radioelektronicke inzenyrstvi 2002-04-01
• Series: Radioengineering
• Online Access: http://www.radioeng.cz/fulltexts/2002/02_01_01_05.pdf

In this paper, a method for analysis and modeling of coplanartransmission interconnect lines that are placed on top ofsilicon-silicon oxide substrates is presented. The potential functionis expressed by series expansions in terms of solutions of the Laplaceequation for each homogeneous region of layered structure. Theexpansion coefficients of different series are related to each otherand to potentials applied to the conductors via boundary conditions. Inthe plane of conductors, boundary conditions are satisfied at Nddiscrete points with Nd being equal to the number of terms in theseries expansions. The resulting system of inhomogeneous linearequations is solved by matrix inversion. No iterations are required. Adiscussion of the calculated line admittance parameters as functions ofwidth of conductors, thickness of the layers, and frequency is given.The interconnect capacitance and conductance per unit length resultsare given and compared with those obtained using full wave solutions,and good agreement have been obtained in all the cases treated.