A Probabilistic Spatial Distribution Model for Wire Faults in Parallel Network-on-Chip Links
High-performance chip multiprocessors contain numerous parallel-processing cores where a fabric devised as a network-on-chip (NoC) efficiently handles their escalating intertile communication demands. Unfortunately, prolonged operational stresses cause accelerated physically induced wearout leading...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Hindawi Limited
2015-01-01
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| Series: | Mathematical Problems in Engineering |
| Online Access: | http://dx.doi.org/10.1155/2015/410172 |