FPGA implementation of impedance-compensated phase-locked loop for HVDC converters

The phase-locked loop (PLL) plays a key role in HVDC systems. Recently, a new type of PLL called the impedance-compensated phase-locked loop (IC-PLL) was introduced to compensate for the voltage drop across the AC network's Thevenin impedance, making the phase locking more robust against transi...

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Main Authors: Yue Yi, Ajinai Ajinai, Aniruddha M.. Gole
Format: Article
Language:English
Published: Wiley 2018-10-01
Series:The Journal of Engineering
Subjects:
Online Access:https://digital-library.theiet.org/content/journals/10.1049/joe.2018.8789
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spelling doaj-7c9e170ea7b745c48d3431a2a16116062021-04-02T15:37:04ZengWileyThe Journal of Engineering2051-33052018-10-0110.1049/joe.2018.8789JOE.2018.8789FPGA implementation of impedance-compensated phase-locked loop for HVDC convertersYue Yi0Ajinai Ajinai1Aniruddha M.. Gole2University of ManitobaTeshmont Consultants LPUniversity of ManitobaThe phase-locked loop (PLL) plays a key role in HVDC systems. Recently, a new type of PLL called the impedance-compensated phase-locked loop (IC-PLL) was introduced to compensate for the voltage drop across the AC network's Thevenin impedance, making the phase locking more robust against transients and harmonics. The IC-PLL has an improved dynamic response as compared with the traditional approaches. However, earlier studies on the IC-PLL are mainly based on off-line simulations. In this study, an actual IC-PLL is constructed in hardware and its performance is investigated by connecting it to a real-time model of a line-commutated converter-based HVDC system on a real-time digital simulator. The proposed IC-PLL is constructed using a field-programmable gate array platform. Paralleled and pipelined structures are implemented on the FPGA to achieve low latency and high speed. The performance of the IC-PLL is tested by exposing it to different type of system disturbances such as sudden step change in power, voltage magnitude change and voltage distortion. Results are compared with the traditional trans-vector PLL. The results show the performance of the IC-PLL is superior.https://digital-library.theiet.org/content/journals/10.1049/joe.2018.8789phase locked loopsHVDC power convertorsdynamic responsefield programmable gate arraysHVDC power transmissiondistortionline-commutated converter-based HVDC systemtraditional trans-vector PLLimpedance-compensated phase-locked loopactual IC-PLLFPGA implementationHVDC convertersvoltage dropAC network Thevenin impedancephase lockingimproved dynamic responseoff-line simulationsreal-time modelfield-programmable gate array platformpipelined structuresparalleled structuressystem disturbancesvoltage distortion
collection DOAJ
language English
format Article
sources DOAJ
author Yue Yi
Ajinai Ajinai
Aniruddha M.. Gole
spellingShingle Yue Yi
Ajinai Ajinai
Aniruddha M.. Gole
FPGA implementation of impedance-compensated phase-locked loop for HVDC converters
The Journal of Engineering
phase locked loops
HVDC power convertors
dynamic response
field programmable gate arrays
HVDC power transmission
distortion
line-commutated converter-based HVDC system
traditional trans-vector PLL
impedance-compensated phase-locked loop
actual IC-PLL
FPGA implementation
HVDC converters
voltage drop
AC network Thevenin impedance
phase locking
improved dynamic response
off-line simulations
real-time model
field-programmable gate array platform
pipelined structures
paralleled structures
system disturbances
voltage distortion
author_facet Yue Yi
Ajinai Ajinai
Aniruddha M.. Gole
author_sort Yue Yi
title FPGA implementation of impedance-compensated phase-locked loop for HVDC converters
title_short FPGA implementation of impedance-compensated phase-locked loop for HVDC converters
title_full FPGA implementation of impedance-compensated phase-locked loop for HVDC converters
title_fullStr FPGA implementation of impedance-compensated phase-locked loop for HVDC converters
title_full_unstemmed FPGA implementation of impedance-compensated phase-locked loop for HVDC converters
title_sort fpga implementation of impedance-compensated phase-locked loop for hvdc converters
publisher Wiley
series The Journal of Engineering
issn 2051-3305
publishDate 2018-10-01
description The phase-locked loop (PLL) plays a key role in HVDC systems. Recently, a new type of PLL called the impedance-compensated phase-locked loop (IC-PLL) was introduced to compensate for the voltage drop across the AC network's Thevenin impedance, making the phase locking more robust against transients and harmonics. The IC-PLL has an improved dynamic response as compared with the traditional approaches. However, earlier studies on the IC-PLL are mainly based on off-line simulations. In this study, an actual IC-PLL is constructed in hardware and its performance is investigated by connecting it to a real-time model of a line-commutated converter-based HVDC system on a real-time digital simulator. The proposed IC-PLL is constructed using a field-programmable gate array platform. Paralleled and pipelined structures are implemented on the FPGA to achieve low latency and high speed. The performance of the IC-PLL is tested by exposing it to different type of system disturbances such as sudden step change in power, voltage magnitude change and voltage distortion. Results are compared with the traditional trans-vector PLL. The results show the performance of the IC-PLL is superior.
topic phase locked loops
HVDC power convertors
dynamic response
field programmable gate arrays
HVDC power transmission
distortion
line-commutated converter-based HVDC system
traditional trans-vector PLL
impedance-compensated phase-locked loop
actual IC-PLL
FPGA implementation
HVDC converters
voltage drop
AC network Thevenin impedance
phase locking
improved dynamic response
off-line simulations
real-time model
field-programmable gate array platform
pipelined structures
paralleled structures
system disturbances
voltage distortion
url https://digital-library.theiet.org/content/journals/10.1049/joe.2018.8789
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