FPGA implementation of impedance-compensated phase-locked loop for HVDC converters

FPGA implementation of impedance-compensated phase-locked loop for HVDC converters

The phase-locked loop (PLL) plays a key role in HVDC systems. Recently, a new type of PLL called the impedance-compensated phase-locked loop (IC-PLL) was introduced to compensate for the voltage drop across the AC network's Thevenin impedance, making the phase locking more robust against transi...

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Bibliographic Details
Main Authors: Yue Yi, Ajinai Ajinai, Aniruddha M.. Gole
Format: Article
Language:English
Published: Wiley 2018-10-01
Series:The Journal of Engineering
Subjects:
phase locked loops
HVDC power convertors
dynamic response
field programmable gate arrays
HVDC power transmission
distortion
line-commutated converter-based HVDC system
traditional trans-vector PLL
impedance-compensated phase-locked loop
actual IC-PLL
FPGA implementation
HVDC converters
voltage drop
AC network Thevenin impedance
phase locking
improved dynamic response
off-line simulations
real-time model
field-programmable gate array platform
pipelined structures
paralleled structures
system disturbances
voltage distortion
Online Access:https://digital-library.theiet.org/content/journals/10.1049/joe.2018.8789

Internet

https://digital-library.theiet.org/content/journals/10.1049/joe.2018.8789

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