A 181 GOPS AKAZE Accelerator Employing Discrete-Time Cellular Neural Networks for Real-Time Feature Extraction

A 181 GOPS AKAZE Accelerator Employing Discrete-Time Cellular Neural Networks for Real-Time Feature Extraction

This paper proposes a real-time feature extraction VLSI architecture for high-resolution images based on the accelerated KAZE algorithm. Firstly, a new system architecture is proposed. It increases the system throughput, provides flexibility in image resolution, and offers trade-offs between speed...

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Bibliographic Details
Main Authors: Guangli Jiang, Leibo Liu, Wenping Zhu, Shouyi Yin, Shaojun Wei
Format: Article
Language:English
Published: MDPI AG 2015-09-01
Series:Sensors
Subjects:
AKAZE
binary feature descriptor
feature extraction
hardware architecture
VLSI implementation
Online Access:http://www.mdpi.com/1424-8220/15/9/22509

Internet

http://www.mdpi.com/1424-8220/15/9/22509

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