A Fault Diagnosis Scheme and Its Quality Issue in Reconfigurable Array Architecture

• Main Author: Yung-Yuan Chen
• Format: Article
• Language: English
• Published: Postgraduate Office, School of Computer Science, Universidad Nacional de La Plata 2006-04-01
• Series: Journal of Computer Science and Technology
• Subjects: fault diagnosis; errors in testing; reconfigurable arrays; switching network; test quality
• Online Access: https://journal.info.unlp.edu.ar/JCST/article/view/822

In this paper, we propose an efficient diagnosis scheme to detect and locate the switching network defects/faults in reconfigurable array architecture. This diagnosis scheme performs the test of switching network based on the scan path and fault intersection test methodology to locate the faults occurring in the switching network. After the diagnosis of switching network, the processing element (PE) test can then be initiated through the good switches and links. Errors in testing that cause a good switch, link or PE to be considered as a bad one is called "killing error". The issue of killing error in testing is addressed and the probability of killing error for our diagnosis technique is analyzed and shown to be extremely low. The significance of this approach is the ability to detect and locate the multiple faults in switches, links, and PEs with low testing circuit overhead, and to offer the good test quality in linear diagnosis time.