CASE STUDY OF EXPLICIT AND IMPLICIT PULSED FLIP FLOPS WITH CONDITIONAL PULSE ENHANCEMENT MECHANISM
In this paper a study of power efficient pulse triggered flip flops was conducted by adopting a pulse control scheme (PCS), named conditional pulse enhancement. The conditional pulse enhancement scheme consists of a simple pass transistor ‘AND’ gate design and a pull up ‘pMOS’. This set up reduc...
| Main Authors: | , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
ICT Academy of Tamil Nadu
2015-10-01
|
| Series: | ICTACT Journal on Microelectronics |
| Subjects: | |
| Online Access: | http://ictactjournals.in/paper/IJME_paper_5_120_123.pdf |
| Summary: | In this paper a study of power efficient pulse triggered flip flops was
conducted by adopting a pulse control scheme (PCS), named
conditional pulse enhancement. The conditional pulse enhancement
scheme consists of a simple pass transistor ‘AND’ gate design and a
pull up ‘pMOS’. This set up reduces circuit complexity and removes the
pulse generation control logic from the critical path, which facilitate a
faster discharge operation as well as improvise the discharge speed
conditionally. In this project, the effect of conditional pulse
enhancement scheme on the power as well as performance of
conventional flip flop such as ep-DCO, ep-CDFF, ip-DCO, are
analyzed. The performance analysis was carried out by adopting
180nm CMOS technology. The simulation results reveal that implicit
flip flops with conditional pulse enhancement scheme outperforms the
conventional flip flops in terms of power and timing characteristics. |
|---|---|
| ISSN: | 2395-1672 2395-1680 |