Hardware Reduction for Lut–Based Mealy FSMs

Hardware Reduction for Lut–Based Mealy FSMs

A method is proposed targeting a decrease in the number of LUTs in circuits of FPGA-based Mealy FSMs. The method improves hardware consumption for Mealy FSMs with the encoding of collections of output variables. The approach is based on constructing a partition for the set of internal states. Each s...

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Bibliographic Details
Main Authors: Barkalov Alexander, Titarenko Larysa, Mielcarek Kamil
Format: Article
Language:English
Published: Sciendo 2018-09-01
Series:International Journal of Applied Mathematics and Computer Science
Subjects:
mealy fsm
synthesis
fpga
lut
partition
encoding collections of output variables
Online Access:https://doi.org/10.2478/amcs-2018-0046

Internet

https://doi.org/10.2478/amcs-2018-0046

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