Hardware Implementation Analysis of Min-Sum Decoders

• Main Authors: Rajagopal Anantharaman, Karibasappa Kwadiki, Vasundara Patel Kerehalli Shankar Rao
• Format: Article
• Language: English
• Published: VSB-Technical University of Ostrava 2019-01-01
• Series: Advances in Electrical and Electronic Engineering
• Subjects: bit error rate (ber); field programmable gate array (fpga); logarithmic sum product (logsp); low density parity check (ldpc); signal to noise ratio (snr); sum product algorithm (spa).
• Online Access: http://advances.utc.sk/index.php/AEEE/article/view/3042
• ISSN: 1336-1376; 1804-3119

The objective of this work is to propose a modified Min-Sum decoding Low Density Parity Check (LDPC) algorithm and perform the hardware implementation analysis of Min-Sum, optimized Min-Sum and modified Min-Sum decoders. The Min-Sum algorithm mainly uses the process of finding the minimum and addition. Hence the number of multiplications is drastically reduced which helps in reducing the complexity of implementation. Adding an optimisation factor to the decoder increases the accuracy and reduces the number of iterations required to compute the decoded message. Hence the process of optimisation reduces the overall decoding time required. Modified Min-Sum algorithm is proposed to further improve the performance by decreasing the number of stages in the decoding process which reduces the complexity in Field Programmable Gate Array (FPGA) implementation.