Hardware Implementation Analysis of Min-Sum Decoders

Hardware Implementation Analysis of Min-Sum Decoders

The objective of this work is to propose a modified Min-Sum decoding Low Density Parity Check (LDPC) algorithm and perform the hardware implementation analysis of Min-Sum, optimized Min-Sum and modified Min-Sum decoders. The Min-Sum algorithm mainly uses the process of finding the minimum and additi...

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Bibliographic Details
Main Authors: Rajagopal Anantharaman, Karibasappa Kwadiki, Vasundara Patel Kerehalli Shankar Rao
Format: Article
Language:English
Published: VSB-Technical University of Ostrava 2019-01-01
Series:Advances in Electrical and Electronic Engineering
Subjects:
bit error rate (ber)
field programmable gate array (fpga)
logarithmic sum product (logsp)
low density parity check (ldpc)
signal to noise ratio (snr)
sum product algorithm (spa).
Online Access:http://advances.utc.sk/index.php/AEEE/article/view/3042

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http://advances.utc.sk/index.php/AEEE/article/view/3042

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