ILP Based Power-Aware Test Time Reduction Using On-Chip Clocking in NoC Based SoC
Network-on-chip (NoC) based system-on-chips (SoC) has been a promising paradigm of core-based systems. It is difficult and challenging to test the individual Intellectual property IP cores of SoC with the constraints of test time and test power. By reusing the on-chip communication network of NoC fo...
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| Series: | Journal of Low Power Electronics and Applications |
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| Online Access: | https://www.mdpi.com/2079-9268/9/2/19 |
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doaj-49d05f20401642929fd02ebc366eb9d92020-11-24T21:53:57ZengMDPI AGJournal of Low Power Electronics and Applications2079-92682019-06-01921910.3390/jlpea9020019jlpea9020019ILP Based Power-Aware Test Time Reduction Using On-Chip Clocking in NoC Based SoCHarikrishna Parmar0Usha Mehta1ECC Department, Nirma University, Ahmedabad 382481, IndiaECC Department, Nirma University, Ahmedabad 382481, IndiaNetwork-on-chip (NoC) based system-on-chips (SoC) has been a promising paradigm of core-based systems. It is difficult and challenging to test the individual Intellectual property IP cores of SoC with the constraints of test time and test power. By reusing the on-chip communication network of NoC for the testing of different cores in SoC, the test time and test cost can be reduced effectively. In this paper, we have proposed a power-aware test scheduling by reusing existing on-chip communication network. On-chip test clock frequencies are used for power efficient test scheduling. In this paper, an integer linear programming (ILP) model is proposed. This model assigns different frequencies to the NoC cores in such a way that it reduces the test time without crossing the power budget. Experimental results on the ITC’02 benchmark SoCs show that the proposed ILP method gives up to 50% reduction in test time compared to the existing method.https://www.mdpi.com/2079-9268/9/2/19NoC based SoCtest schedulingtest time reductiontest bus architecturetest powertest clock frequencyILP |
| collection |
DOAJ |
| language |
English |
| format |
Article |
| sources |
DOAJ |
| author |
Harikrishna Parmar Usha Mehta |
| spellingShingle |
Harikrishna Parmar Usha Mehta ILP Based Power-Aware Test Time Reduction Using On-Chip Clocking in NoC Based SoC Journal of Low Power Electronics and Applications NoC based SoC test scheduling test time reduction test bus architecture test power test clock frequency ILP |
| author_facet |
Harikrishna Parmar Usha Mehta |
| author_sort |
Harikrishna Parmar |
| title |
ILP Based Power-Aware Test Time Reduction Using On-Chip Clocking in NoC Based SoC |
| title_short |
ILP Based Power-Aware Test Time Reduction Using On-Chip Clocking in NoC Based SoC |
| title_full |
ILP Based Power-Aware Test Time Reduction Using On-Chip Clocking in NoC Based SoC |
| title_fullStr |
ILP Based Power-Aware Test Time Reduction Using On-Chip Clocking in NoC Based SoC |
| title_full_unstemmed |
ILP Based Power-Aware Test Time Reduction Using On-Chip Clocking in NoC Based SoC |
| title_sort |
ilp based power-aware test time reduction using on-chip clocking in noc based soc |
| publisher |
MDPI AG |
| series |
Journal of Low Power Electronics and Applications |
| issn |
2079-9268 |
| publishDate |
2019-06-01 |
| description |
Network-on-chip (NoC) based system-on-chips (SoC) has been a promising paradigm of core-based systems. It is difficult and challenging to test the individual Intellectual property IP cores of SoC with the constraints of test time and test power. By reusing the on-chip communication network of NoC for the testing of different cores in SoC, the test time and test cost can be reduced effectively. In this paper, we have proposed a power-aware test scheduling by reusing existing on-chip communication network. On-chip test clock frequencies are used for power efficient test scheduling. In this paper, an integer linear programming (ILP) model is proposed. This model assigns different frequencies to the NoC cores in such a way that it reduces the test time without crossing the power budget. Experimental results on the ITC’02 benchmark SoCs show that the proposed ILP method gives up to 50% reduction in test time compared to the existing method. |
| topic |
NoC based SoC test scheduling test time reduction test bus architecture test power test clock frequency ILP |
| url |
https://www.mdpi.com/2079-9268/9/2/19 |
| work_keys_str_mv |
AT harikrishnaparmar ilpbasedpowerawaretesttimereductionusingonchipclockinginnocbasedsoc AT ushamehta ilpbasedpowerawaretesttimereductionusingonchipclockinginnocbasedsoc |
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