ILP Based Power-Aware Test Time Reduction Using On-Chip Clocking in NoC Based SoC

ILP Based Power-Aware Test Time Reduction Using On-Chip Clocking in NoC Based SoC

Network-on-chip (NoC) based system-on-chips (SoC) has been a promising paradigm of core-based systems. It is difficult and challenging to test the individual Intellectual property IP cores of SoC with the constraints of test time and test power. By reusing the on-chip communication network of NoC fo...

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Bibliographic Details
Main Authors: Harikrishna Parmar, Usha Mehta
Format: Article
Language:English
Published: MDPI AG 2019-06-01
Series:Journal of Low Power Electronics and Applications
Subjects:
NoC based SoC
test scheduling
test time reduction
test bus architecture
test power
test clock frequency
ILP
Online Access:https://www.mdpi.com/2079-9268/9/2/19

Internet

https://www.mdpi.com/2079-9268/9/2/19

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