Key Process Approach Recommendation for 5 nm Logic Process Flow with EUV Photolithography

• Main Authors: Yushu Yang, Yanli Li, Qiang Wu, Jianjun Zhu, Shoumian Chen
• Format: Article
• Language: English
• Published: JommPublish 2020-03-01
• Series: Journal of Microelectronic Manufacturing
• Subjects: 5 nm logic process; euv; metal gate cut; sac; bac; self-aligned lele
• Online Access: http://www.jommpublish.org/p/48/

5 nm logic process is the current leading-edge technology which is under development in world-wide leading foundries. In a typical 5 nm logic process, the Fin pitch is 22~27 nm, the contact-poly pitch (CPP) is 48~55 nm, and the minimum metal pitch (MPP) is around 30~36 nm. Due to the fact that these pitches are much smaller than the resolution capability of 193 nm immersion lithography, it is also the first generation which adopts EUV photolithography technology on a large-scale where the process flow can be simplified by single exposure method from more than 10 layers. Relentless scaling brings big challenges to process integration and pushes each process module to the physical and material limit. Therefore, the success of process development will largely depend on careful balance the pros and cons to achieve both performance and yield targets. In the paper, we discussed the advantages and disadvantages of different process approaches for key process loops for 5 nm logic process flow, including dummy poly cut versus metal gate cut approaches in the metal gate loops, self-aligned contact (SAC) versus brutally aligned contact (BAC) approaches, and also introduced the self-aligned double patterning approach in the lower metal processes. Based on the above evaluation, we will provide a recommendation for module’s process development.