Electrical Characteristics of LDD and LDD-Free FinFET Devices of Dimension Compatible With 14 nm Technology Node

• Main Authors: Yuchen Du, Md Khaled Hassan, Ri-an Zhao, Xinggong Wan, Manoj Joshi
• Format: Article
• Language: English
• Published: IEEE 2020-01-01
• Series: IEEE Journal of the Electron Devices Society
• Subjects: FinFET; 14nm; LDD; Vtsat mismatch; SS; DIBL
• Online Access: https://ieeexplore.ieee.org/document/9206537/
• ISSN: 2168-6734

FinFET devices with and without LDD implantation has been studied for dimensions compatible with leading 14nm technology node. Devices without LDD have better electrostatic characteristics with SS = 65mV/dec and DIBL = 33mV. The nFET transistors with no LDD have device Vtsat mismatch reduction by 20%, together with retained device reliability of HCI as compared to devices with LDD. A full range of device Vtsat flavors is enabled in this experiment, presenting excellent device performances at different operating voltages of 0.55V, 0.8V and 1.2V. All results indicates that devices with no LDD and one less mask in FinFET architecture achieve lower cost, compelling performance and area scaling compared to devices with LDD, for high performance and low power applications.