A Compact 32-Pixel TU-Oriented and SRAM-Free Intra Prediction VLSI Architecture for HEVC Decoder

A Compact 32-Pixel TU-Oriented and SRAM-Free Intra Prediction VLSI Architecture for HEVC Decoder

In the High Efficiency Video Coding (HEVC), a variety of CU sizes and intra prediction modes significantly improve coding efficiency, but also bring higher computational complexity. This paper proposes a new compact VLSI architecture for HEVC intra prediction, which is geared towards 8K video decodi...

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Bibliographic Details
Main Authors: Yibo Fan, Genwei Tang, Xiaoyang Zeng
Format: Article
Language:English
Published: IEEE 2019-01-01
Series:IEEE Access
Subjects:
32-pixel
TU-oriented
SRAM-free
HEVC intra prediction
8K decoder
Online Access:https://ieeexplore.ieee.org/document/8865037/

Internet

https://ieeexplore.ieee.org/document/8865037/

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