GAAFET Versus Pragmatic FinFET at the 5nm Si-Based CMOS Technology Node

GAAFET Versus Pragmatic FinFET at the 5nm Si-Based CMOS Technology Node

Speed and power performances of Si-based stacked-nanowire gate-all-around (GAA) FETs and pragmatic ultra-thin-fin FETs at the 5nm CMOS technology node are projected, compared, and physically explained based on 3-D numerical simulations. The respective device domains are also used to compare integrat...

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Bibliographic Details
Main Authors: Ya-Chi Huang, Meng-Hsueh Chiang, Shui-Jinn Wang, Jerry G. Fossum
Format: Article
Language:English
Published: IEEE 2017-01-01
Series:IEEE Journal of the Electron Devices Society
Subjects:
FinFET
GAAFET
G-S/D underlap
ultra-thin body
Online Access:https://ieeexplore.ieee.org/document/7890390/

Internet

https://ieeexplore.ieee.org/document/7890390/

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