White Light Interference Solution for Novel 3D NAND VIA Dishing Metrology

White Light Interference Solution for Novel 3D NAND VIA Dishing Metrology

In traditional 3D NAND design, peripheral circuit accounts for 20-30% of the chip real-estate, which reduces the memory density of flash memory. As 3D NAND technology stacks to 128 layers or higher, peripheral circuits may account for more than 50% of the overall chip area. On the contrast, the Xtac...

Full description

Bibliographic Details
Main Authors: Xiaoye Ding, Sicong Wang, Yi Zhou, Yanzhong Ma, Le Yang, Chi Chen
Format: Article
Language:English
Published: JommPublish 2019-12-01
Series:Journal of Microelectronic Manufacturing
Subjects:
wli
dishing
metrology
3d nand
bonding
Online Access:http://www.jommpublish.org/p/42/#

Internet

http://www.jommpublish.org/p/42/#

Similar Items