High-Resolution Digital-to-Time Converter Implemented in an FPGA Chip

This paper presents the design and implementation of a new digital-to-time converter (DTC). The obtained resolution is 1.02 ps, and the dynamic range is about 590 ns. The experimental results indicate that the measured differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.17~+0.13 L...

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Bibliographic Details
Main Authors: Hai Wang, Min Zhang, Yan Liu
Format: Article
Language:English
Published: MDPI AG 2017-01-01
Series:Applied Sciences
Subjects:
Online Access:http://www.mdpi.com/2076-3417/7/1/52