Hardware Implementation Of Line Clipping A lgorithm By Using FPGA
<p>The computer graphics system performance is increasing faster than any other computing application. Algorithms for line clipping against convex polygons and lines have been studied for a long time and many research papers have been published so far. In spite of the latest graphical hardware...
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| Format: | Article |
| Language: | English |
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Tikrit University
2013-04-01
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| Series: | Tikrit Journal of Engineering Sciences |
| Subjects: | |
| Online Access: | http://www.tj-es.com/ojs/index.php/tjes/article/view/133 |
| Summary: | <p>The computer graphics system performance is increasing faster than any other computing application. Algorithms for line clipping against convex polygons and lines have been studied for a long time and many research papers have been published so far. In spite of the latest graphical hardware development and significant increase of performance the clipping is still a bottleneck of any graphical system. So its implementation in hardware is essential for real time applications. In this paper clipping operation is discussed and a hardware implementation of the line clipping algorithm is presented and finally formulated and tested using Field Programmable Gate Arrays (FPGA). The designed hardware unit consists of two parts : the first is positional code generator unit and the second is the clipping unit. Finally it is worth mentioning that the designed unit is capable of clipping (232524 ) line segments per second. </p><p> <strong></strong></p> |
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| ISSN: | 1813-162X 2312-7589 |