Design of high speed and low offset dynamic latch comparator in 0.18 µm CMOS process.

Design of high speed and low offset dynamic latch comparator in 0.18 µm CMOS process.

The cross-coupled circuit mechanism based dynamic latch comparator is presented in this research. The comparator is designed using differential input stages with regenerative S-R latch to achieve lower offset, lower power, higher speed and higher resolution. In order to decrease circuit complexity,...

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Main Authors: Labonnah Farzana Rahman, Mamun Bin Ibne Reaz, Chia Chieu Yin, Mohammad Alauddin Mohammad Ali, Mohammad Marufuzzaman
Format: Article
Language:English
Published: Public Library of Science (PLoS) 2014-01-01
Series:PLoS ONE
Online Access:http://europepmc.org/articles/PMC4191981?pdf=render
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spelling doaj-2a4247183674423ca63e743889065da42020-11-24T21:50:43ZengPublic Library of Science (PLoS)PLoS ONE1932-62032014-01-01910e10863410.1371/journal.pone.0108634Design of high speed and low offset dynamic latch comparator in 0.18 µm CMOS process.Labonnah Farzana RahmanMamun Bin Ibne ReazChia Chieu YinMohammad Alauddin Mohammad AliMohammad MarufuzzamanThe cross-coupled circuit mechanism based dynamic latch comparator is presented in this research. The comparator is designed using differential input stages with regenerative S-R latch to achieve lower offset, lower power, higher speed and higher resolution. In order to decrease circuit complexity, a comparator should maintain power, speed, resolution and offset-voltage properly. Simulations show that this novel dynamic latch comparator designed in 0.18 µm CMOS technology achieves 3.44 mV resolution with 8 bit precision at a frequency of 50 MHz while dissipating 158.5 µW from 1.8 V supply and 88.05 µA average current. Moreover, the proposed design propagates as fast as 4.2 nS with energy efficiency of 0.7 fJ/conversion-step. Additionally, the core circuit layout only occupies 0.008 mm2.http://europepmc.org/articles/PMC4191981?pdf=render
collection DOAJ
language English
format Article
sources DOAJ
author Labonnah Farzana Rahman
Mamun Bin Ibne Reaz
Chia Chieu Yin
Mohammad Alauddin Mohammad Ali
Mohammad Marufuzzaman
spellingShingle Labonnah Farzana Rahman
Mamun Bin Ibne Reaz
Chia Chieu Yin
Mohammad Alauddin Mohammad Ali
Mohammad Marufuzzaman
Design of high speed and low offset dynamic latch comparator in 0.18 µm CMOS process.
PLoS ONE
author_facet Labonnah Farzana Rahman
Mamun Bin Ibne Reaz
Chia Chieu Yin
Mohammad Alauddin Mohammad Ali
Mohammad Marufuzzaman
author_sort Labonnah Farzana Rahman
title Design of high speed and low offset dynamic latch comparator in 0.18 µm CMOS process.
title_short Design of high speed and low offset dynamic latch comparator in 0.18 µm CMOS process.
title_full Design of high speed and low offset dynamic latch comparator in 0.18 µm CMOS process.
title_fullStr Design of high speed and low offset dynamic latch comparator in 0.18 µm CMOS process.
title_full_unstemmed Design of high speed and low offset dynamic latch comparator in 0.18 µm CMOS process.
title_sort design of high speed and low offset dynamic latch comparator in 0.18 µm cmos process.
publisher Public Library of Science (PLoS)
series PLoS ONE
issn 1932-6203
publishDate 2014-01-01
description The cross-coupled circuit mechanism based dynamic latch comparator is presented in this research. The comparator is designed using differential input stages with regenerative S-R latch to achieve lower offset, lower power, higher speed and higher resolution. In order to decrease circuit complexity, a comparator should maintain power, speed, resolution and offset-voltage properly. Simulations show that this novel dynamic latch comparator designed in 0.18 µm CMOS technology achieves 3.44 mV resolution with 8 bit precision at a frequency of 50 MHz while dissipating 158.5 µW from 1.8 V supply and 88.05 µA average current. Moreover, the proposed design propagates as fast as 4.2 nS with energy efficiency of 0.7 fJ/conversion-step. Additionally, the core circuit layout only occupies 0.008 mm2.
url http://europepmc.org/articles/PMC4191981?pdf=render
work_keys_str_mv AT labonnahfarzanarahman designofhighspeedandlowoffsetdynamiclatchcomparatorin018μmcmosprocess
AT mamunbinibnereaz designofhighspeedandlowoffsetdynamiclatchcomparatorin018μmcmosprocess
AT chiachieuyin designofhighspeedandlowoffsetdynamiclatchcomparatorin018μmcmosprocess
AT mohammadalauddinmohammadali designofhighspeedandlowoffsetdynamiclatchcomparatorin018μmcmosprocess
AT mohammadmarufuzzaman designofhighspeedandlowoffsetdynamiclatchcomparatorin018μmcmosprocess
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