Design of high speed and low offset dynamic latch comparator in 0.18 µm CMOS process.

Design of high speed and low offset dynamic latch comparator in 0.18 µm CMOS process.

The cross-coupled circuit mechanism based dynamic latch comparator is presented in this research. The comparator is designed using differential input stages with regenerative S-R latch to achieve lower offset, lower power, higher speed and higher resolution. In order to decrease circuit complexity,...

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Bibliographic Details
Main Authors: Labonnah Farzana Rahman, Mamun Bin Ibne Reaz, Chia Chieu Yin, Mohammad Alauddin Mohammad Ali, Mohammad Marufuzzaman
Format: Article
Language:English
Published: Public Library of Science (PLoS) 2014-01-01
Series:PLoS ONE
Online Access:http://europepmc.org/articles/PMC4191981?pdf=render

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http://europepmc.org/articles/PMC4191981?pdf=render

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