Probabilistic modeling of noise transfer characteristics in digital circuits
Device scaling, the driving force of CMOS technology, led to continuous decrease in the energy level representing logic states. The resulting small noise margins in combination with increasing problems regarding the supply voltage stability and process variability creates a design conflict between e...
Main Authors: | J. Schleifer, T. Coenen, A. Elkammar, T. G. Noll |
---|---|
Format: | Article |
Language: | deu |
Published: |
Copernicus Publications
2011-08-01
|
Series: | Advances in Radio Science |
Online Access: | http://www.adv-radio-sci.net/9/269/2011/ars-9-269-2011.pdf |
Similar Items
-
A probabilistic testability measure model and program for digital circuits
by: HUANG, WEI-BIN, et al.
Published: (1987) -
An investigation into a probabilistic digital integrated circuit testability analysis
by: Franco, Piero
Published: (2015) -
Digital Circuit Design of Wavelet- Probabilistic Network Algorithm for Power Systems
by: Chia-Hao Wang, et al.
Published: (2005) -
Design and Implementation of Noise-Tolerant Digital CMOS Circuits
by: I-Chyn Wey, et al.
Published: (2008) -
Obfuscation of Probabilistic Circuits and Applications
by: Ananth, Prabhanjan, et al.
Published: (2021)