Probabilistic modeling of noise transfer characteristics in digital circuits
Device scaling, the driving force of CMOS technology, led to continuous decrease in the energy level representing logic states. The resulting small noise margins in combination with increasing problems regarding the supply voltage stability and process variability creates a design conflict between e...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | deu |
| Published: |
Copernicus Publications
2011-08-01
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| Series: | Advances in Radio Science |
| Online Access: | http://www.adv-radio-sci.net/9/269/2011/ars-9-269-2011.pdf |
| Summary: | Device scaling, the driving force of CMOS technology, led to continuous
decrease in the energy level representing logic states. The resulting small
noise margins in combination with increasing problems regarding the supply
voltage stability and process variability creates a design conflict between
efficiency and reliability. This conflict is expected to rise more in future
technologies. Current research approaches on fault-tolerance architectures
and countermeasures at circuit level, unfortunately, cause a significant
area and energy penalty without guaranteeing absence of errors. To overcome
this problem, it seems to be attractive to tolerate bit errors at circuit
level and employ error handling methods at higher system levels. To do this,
an estimate of the bit error rate (BER) at circuit level is necessary. Due
to the size of the circuits, Monte Carlo simulation suffers from impractical
runtimes. Therefore the needed modeling scheme is proposed. The model allows
a probabilistic estimation of error rates at circuit level taking into
account statistical effects ranging from supply noise and electromagnetic
coupling to process variability within reasonable runtimes. |
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| ISSN: | 1684-9965 1684-9973 |