Deep sub-micron ESD GGNMOS layout design and optimization
In the field of integrated circuits, ESD (Electro Static Discharge) has always been a rather serious problem of reliability. Enhanced ESD tolerance of IC chips became a focus of research on IC failure protection design. The thesis is better to solve the multi-fingered non-uniform conduction of ESD d...
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| Format: | Article |
| Language: | English |
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EDP Sciences
2018-01-01
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| Series: | MATEC Web of Conferences |
| Online Access: | https://doi.org/10.1051/matecconf/201819804009 |