The design of scalar AES Instruction Set Extensions for RISC-V
Secure, efficient execution of AES is an essential requirement on most computing platforms. Dedicated Instruction Set Extensions (ISEs) are often included for this purpose. RISC-V is a (relatively) new ISA that lacks such a standardized ISE. We survey the state-of-the-art industrial and academic IS...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Ruhr-Universität Bochum
2020-12-01
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| Series: | Transactions on Cryptographic Hardware and Embedded Systems |
| Subjects: | |
| Online Access: | https://tches.iacr.org/index.php/TCHES/article/view/8729 |