800 MB/s DDR NAND Flash Memory Multi-Chip Package With Source-Synchronous Interface for Point-to-Point Ring Topology

800 MB/s DDR NAND Flash Memory Multi-Chip Package With Source-Synchronous Interface for Point-to-Point Ring Topology

A 256 Gb NAND flash memory multi-chip package (MCP) includes eight stacked 32 Gb 2 bit/cell multi-level cell (MLC) die and an 11.6 mm<sup>2</sup> HyperLink NAND bridge chip providing four internal NAND channels for concurrent memory operations. The bridge chip provides an external 1.2 V...

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Bibliographic Details
Main Authors: Peter Gillingham, David Chinn, Eric Choi, Jin-Ki Kim, Don Macdonald, Hakjune Oh, Hong-Beom Pyeon, Roland Schuetz
Format: Article
Language:English
Published: IEEE 2013-01-01
Series:IEEE Access
Subjects:
Disk drives
high speed integrated circuits
nonvolatile memory
Online Access:https://ieeexplore.ieee.org/document/6681893/

Internet

https://ieeexplore.ieee.org/document/6681893/

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