Delay Insensitive Ternary CMOS Logic for Secure Hardware

Delay Insensitive Ternary CMOS Logic for Secure Hardware

As digital circuit design continues to evolve due to progress of semiconductor processes well into the sub 100 nm range, clocked architectures face limitations in a number of cases where clockless asynchronous architectures generate less noise and produce less electro-magnetic interference (EMI). Th...

Full description

Bibliographic Details
Main Authors: Ravi S. P. Nair, Scott C. Smith, Jia Di
Format: Article
Language:English
Published: MDPI AG 2015-09-01
Series:Journal of Low Power Electronics and Applications
Subjects:
Asynchronous Logic
Delay Insensitive Logic
Ternary Logic
Digital Design
NCL
Secure Circuits
Online Access:http://www.mdpi.com/2079-9268/5/3/183

Internet

http://www.mdpi.com/2079-9268/5/3/183

Similar Items