Symbol Synchronization for SDR Using a Polyphase Filterbank Based on an FPGA
This paper is devoted to the proposal of a highly efficient symbol synchronization subsystem for Software Defined Radio. The proposed feedback phase-locked loop timing synchronizer is suitable for parallel implementation on an FPGA. The polyphase FIR filter simultaneously performs matched-filtering...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Spolecnost pro radioelektronicke inzenyrstvi
2015-09-01
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| Series: | Radioengineering |
| Subjects: | |
| Online Access: | http://www.radioeng.cz/fulltexts/2015/15_03_0772_0782.pdf |