ESD full chip simulation: HBM and CDM requirements and simulation approach
Verification of ESD safety on full chip level is a major challenge for IC design. Especially phenomena with their origin in the overall product setup are posing a hurdle on the way to ESD safe products. For stress according to the Charged Device Model (CDM), a stumbling stone for a simulation based...
| Main Authors: | , , , |
|---|---|
| Format: | Article |
| Language: | deu |
| Published: |
Copernicus Publications
2008-05-01
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| Series: | Advances in Radio Science |
| Online Access: | http://www.adv-radio-sci.net/6/245/2008/ars-6-245-2008.pdf |